1. Field of the Invention
The present invention relates to a microprocessor having condition execution instructions in which execution of an instruction is controlled by using a condition execution field included in a part of the instruction.
2. Description of Related Art
There are methods such as a condition execution method and a speculative execution method which increase performance of a microprocessor by reducing a branch penalty in a pipeline execution.
FIG. 1 is an explanation diagram showing an example of an instruction format used in a conventional RISC microprocessor shown on pages 2-29 in a family data manual of ARM (ACORN RISC MACHINE) by VLSI technology corp., for example. As shown in FIG. 1, a condition execution instruction used in this conventional microprocessor has a 4-bit condition execution field of bits #28-31. This condition execution field and a negative flag (N), a zero flag (Z), a carry flag (C) and an overflow flag (V) determine whether or not an instruction will be executed. However, because each flag to be used for decision of this condition execution is a dedicated flag, the range of a condition execution in the conventional microprocessor is limited.
FIG. 2 is an explanation diagram showing an instruction format used in another conventional microprocessor disclosed in Japanese laid-open publication number JP-A-182165.
In FIG. 2, the reference number 301 designates a condition execution field in which execution conditions will be set or described, and 302 denotes an operation field as an operation section. In the condition execution field 301, the reference numbers 303 and 304 indicate Cv0 and Cd0 bits which are related to the flag #0 in the microprocessor, respectively. The reference numbers 305 and 306 designate Cv1 and Cd1 bits which are related to the flag #1 in the microprocessor. The reference numbers 307 and 308 denote Cv2 and Cd2 bits which are related to the flag #2 in the microprocessor.
FIG. 3 is an explanation diagram showing the connection between the Cv and Cd bits and their meanings. In FIG. 3, the Cv bit includes the Cv0 bit 303, the Cv1 bit 305 and the Cv2 bit 307, as have been shown in FIG. 2. The Cd bit shown in FIG. 3 includes the Cd0 bit 304, the Cd1 bit 306 and the Cd2 bit 308, as have been shown in FIG. 2. As shown in FIG. 3, in the case where both values of the Cv0 bit 303 and the Cd0 bit 304 in the condition execution field 301 are set to 1, the condition is established so that an instruction will be executed when the value of the flag #0 is true. In the case where both values, the Cv0 bit 303 and the Cd0 bit 304 are set to 1 and zero, respectively, the condition is established so that an instruction will be executed when the value of the flag #0 is false. When both values of the Cv0 bit 303 is set to 0, the condition is established so that an instruction will be executed in spite of the state of the value of the flag #0.
The Cv1 bit 305, the Cd1 bit 306 and the flag #1 can be checked by using the relationship, as shown in FIG. 3, whether or not the execution condition to execute an instruction is established. The Cv2 bit 307, the Cd2 bit 308 and the flag #2 also be checked by using the relationship, as shown in FIG. 3, whether or not an execution condition to execute an instruction is established.
The Cv bit is a bit used for judging effectively of the condition because the judgement of true or false will be performed or not according to the value of the Cv bit. In addition, the Cd bit is a bit used for judging a value because the judgement whether it is true or false will be performed according to the value of the Cd bit.
Next, the operation of the conventional microprocessor described above will now be explained.
The conventional microprocessor can control whether or not an instruction indicated by the value stored in the operation field 302 will be executed according to the condition execution field 301 in the instruction format 300. For example, when the value "111111" is set in the condition execution field 301, the microprocessor executes the instruction indicated by the operation field 302 when all of the flag #0, the flag #1 and the flag #2 are true.
Each of the flag #0, the flag #1 and the flag #2 uses a 1-bit, for example, the value "true" can be expressed by the value "1" and the value "false" is expressed by the value "0". In the microprocessor disclosed in Japanese laid-open publication number JP-A-7-182165, each of the flag #0, the flag #1 and the flag #2 is expressed by using a 2-bit value in order to indicate the true state, the false state and the undecided state. For example, when there is a flag whose value indicates the undecided state and other conditions are established, the instruction designated by the operation field 302 will be executed. In this case, the execution result is written into a shadow register file which is different from the general registers. When all conditions are established, at this time, the content stored in the shadow register file is written into the general register files. Thereby, speculative execution is realized. In addition, Japanese laid-open publication number JP-A-7-182165 discloses a microprocessor having m-flags (m&gt;3) in order to increase condition numbers.
Since the conventional microprocessors having condition execution instructions have the configurations and they perform as described above, the range of condition execution can be expanded, but it requires the 6-bit condition execution field 301 for 3-flags, for example. Thus, the conventional microprocessor has a drawback that the bit size or the number of bits in the condition execution field 301 is big or large.
In addition, in the microprocessor disclosed in the Japanese laid-open publication number JP-A-2-22873, an encoded value used for deciding whether or not a branch instruction or a jump instruction is performed is stored in a register and a decoded value as a value used for judging whether or not the branch instruction or a jump instruction is performed is provided from the register. However, the conventional microprocessor shown in the Japanese laid-open publication number JP-A-2-22873 does not disclose any configuration of the condition execution field in an instruction.